Chan-Ho Kye
System Semiconductor
Position
Assistant Professor
Tel.
+82 31-750-5286
chkye@gachon.ac.kr
Location
#5-6, College of Semiconductor / #211B, College of Semiconductor
About:
The CHIPER Lab conducts research on high-speed analog and mixed-signal integrated circuits for next-generation semiconductor systems. Our main research areas include high-speed ADCs, PLL/CDR circuits, SerDes, memory interfaces, high-speed transceivers, and data converters. Our group covers the complete IC design process, including architecture development, transistor-level circuit design, layout implementation, chip fabrication, measurement, and silicon verification. In particular, we focus on high-speed data converters and next-generation memory interface circuits to develop practical semiconductor technologies for industrial applications. The CHIPER Lab aims to provide technological solutions for a better future through innovative circuit design and silicon-proven research, while nurturing global leaders for the next-generation semiconductor industry.
Education:
16.03 ~ 21.08 Seoul National University Department of Electrical and Computer Engineering Doctor
10.03 ~ 16.02 Korea University Department of Electrical Engineering B.S.
Experience:
23.10 ~ 25.02 The University of Suwon, Department of Semiconductor Engineering Assistant Professor
23.01 ~ 23.09 The University of Michigan Department of Electrical and Computer Engineering Postdoctoral researcher
22.01 ~ 22.12 Swiss Federal Institute of Technology Lausanne (EPFL) Institute of Electrical and Micro Engineering Postdoctoral researcher
21.09 ~ 21.11 Seoul National University Inter-university Semiconductor Research Center Postdoctoral researcher
Honors & Specialities:
Thesis
2026 A 48 Gb/s PAM-4 Transceiver with Transition Boosting and RLM Calibration for Next-Generation Memory Interface Testing
2025 A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology
2024 Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC
2024 Integrated Multifunctional Laser-Induced-Graphene Sensor with an Open-Source AFE for Fast Prototyping of Flexible Wearables
2024 A 4.5-to-14 GHz PLL-Based Clock Driver with Wide-Range 3-Shaped LC-VCOs for GDDR6 DRAM Test
2020 A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces
2020 A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS
2020 Balancing Scheme for Phase Current and Flying-Capacitor Voltage in Three-Level DC-DC Converter
2019 A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator
Academic activities
2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), Hiroshima, Japan
2024 IEEE International Symposium on Integrated Circuits and Systems (ISICAS), New Delhi, India
2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Okinawa, Japan
2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), Haikou, China
2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), Taipei, Taiwan
2019 IEEE Symposium on VLSI Circuits (VLSI Symposium), Kyoto, Japan
2019 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA
2018 International Conference on Electronics, Information, and Communication (ICEIC), Hawaii, USA
Patent
2025 Test aid units
2022 Integrated circuit and memory
2024 A test aid unit
2018 Integrated circuit and memory
