About:
Education:
2000.09 ~ 2007.05 Texas A&M University Department of Electrical Engineering Ph.D.
1991.03 ~ 1993.02 SEOUL UNIVERSITY Department of Physices M.S.
1987.02 ~ 1991.02 SEOUL UNIVERSITY Department of Physices B.S.
Experience:
2025.03 ~ Current GACHON University, Department of SEMICONDUCTOR DISPLAY Semiconductor
Design Visiting Professor
2012.01 ~ 2025.02 SAMSUNG ELECTRONICS Product Planning Team Principal Engineer
2007.6 ~ 2011.12 SAMSUNG ELECTRONICS ATD Principal Engineer
1993.01 ~ 2000.07 HUNDAI ELECTRONICS Flash Memory Development Team Senior Engineer
Honors & Specialities:
2012.02 A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth, 2012 ISSCC, San Francisco, USA
2011.02 A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW, 2011 ISSCC, San Francisco, USA
2007.04 Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits, 2007 VLSID, Bangalore, India
2006.11 Timing Failure Analysis of Commercial CPUs Under Operating Stress, 2006 DFT, Washington D.C., USA
2005.11 Delay Failure Rate Estimation: An Experimental Approach, 2004 LATW, Cartagena, Colombia
