About:
Education:
00.9 ~ 07.5 Texas A&M University Department of Electrical Engineering Ph.D.
91.3 ~ 93.2 SEOUL UNIVERSITY Department of Physices M.S.
87.2 ~ 91.2 SEOUL UNIVERSITY Department of Physices B.S.
Experience:
25.3 ~ 현재 GACHON University, Department of SEMICONDUCTOR DISPLAY Semiconductor
Design Visiting Professor
12.1 ~ 25.2 SAMSUNG ELECTRONICS Product Planning Team Principal Engineer
07.6 ~ 11.12 SAMSUNG ELECTRONICS ATD Principal Engineer
93.1 ~ 00.7 HUNDAI ELECTRONICS Flash Memory Development Team Senior Engineer
Honors & Specialities:
2012.2 A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth, 2012 ISSCC, San Francisco, USA
2011.2 A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW, 2011 ISSCC, San Francisco, USA
2007.4 Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits, 2007 VLSID, Bangalore, India
2006.11 Timing Failure Analysis of Commercial CPUs Under Operating Stress, 2006 DFT, Washington D.C., USA
2005.11 Delay Failure Rate Estimation: An Experimental Approach, 2004 LATW, Cartagena, Colombia
