About:
Next-generation Semiconductor Design Lab
Education:
90.3 ~ 92.8 KAIST Department of Electrical Engineering Ph. D.
88.3 ~ 90.2 KAIST Department of Electrical Engineering Master
84.3 ~ 88.2 Yonsei University Department of Electrical Engineering B.S.
Experience:
20.03 ~ 23.09 Abov Semiconductor Semiconductor Design CTO/EVP
07.03 ~ 20.02 Samsung Electronics Co., Ltd Semiconductor Design Sr. Vice President
03.01 ~ 07.02 Sun Microsystems Semiconductor Design Manager
01.01 ~ 02.12 Luminous Networks Semiconductor Design Sr. MTS
97.07 ~ 01.01 Sun Microsystems Semiconductor Design Staff Engineer
Honors & Specialities:
2015.02 “20nm high-k metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor”, IEEE Int. Solid-State Cir. Conf. (ISSCC)
2013.02 "28nm high-k metal gate heterogeneous quad-core CPUs for high-performance and energy efficient mobile application processor", IEEE Int. Solid-State Cir. Conf. (ISSCC)
2017.01 "Test generation methods for utilization improvement of hardware-accelerated simulation
platforms", IEEE Design & Test
2013.04 "A 1.6 GHz quad-core application processor manufactured in 32 nm high-k metal gate process for smart mobile devices", IEEE Comm. Magazine
2015.08 "Technological trends and upcoming challenges of mobile SoC design", Keynote Speech at IEEE Midwest Symposium on Circuits and Systems
